Kubilay Atasu

I am an Associate Professor at the Delft University of Technology, where I am affiliated with the Data Intensive Systems Section of the Department of Software Technology.

I am a Senior Member of IEEE and the principal investigator of a Swiss National Science Foundation (SNSF) project aimed at building scalable graph ML solutions for financial crime analysis. My research interests include graph algorithms, graph neural networks, parallel computing, and hardware acceleration using FPGAs and GPUs.

Before joining TU Delft, I was a Senior Research Scientist at IBM Research – Zurich , where I spent 15 years. Importantly, I led a global IBM Research Challenge on scalable and automated graph machine learning from 2021 to 2023, which led to new AI-powered real-time transaction monitoring capabilities in IBM’s mainframe software solutions (specifically, in the AI Toolkit for IBM Z and LinuxOne) as well as an IBM Outstanding Technical Accomplishment Award.

My earlier work at IBM focused on design of hardware accelerators and domain-specific compilers for hardware accelerators. Notably, I contributed to the design and development of the pattern-matching engine of IBM PowerEN (Power Edge-of-Network) processor for deep packet inspection at wire speeds. In addition, I led design and development of FPGA-accelerated text analytics and GPU-accelerated semantic similarity search solutions, achieving 10- to 1000-fold performance improvements.

While with IBM Research – Zurich, I also taught at the University of Tübingen and did a sabbatical at the Sabanci University, Istanbul. Furthermore, I served in the technical program committees or organizing committees of more than 60 scientific conferences. I was the program chair of IEEE ASAP 2013 conference and the general chair of the IEEE ASAP 2014 conference.

Before joining IBM Research – Zurich, I was with the École Polytechnique Fédérale de Lausanne (2002–2003), Bogazici University Istanbul (2003–2005), and Imperial College London (2005–2008), where I worked on design automation of application-specific microprocessors, and obtained two best paper awards for this work (at the DAC 2003 and at the IEEE ASAP 2008 conferences).